They are stuck with single-thread performance, as there is still a lot of COBOL code out there, that just don't run multi-threaded.
ITJungle.com writes:
Just based on clock speeds alone and the improved efficiency that IBM is promising in terms of instructions processed per clock comparing Power5 and Power6 chips, I would have expected a lot more oomph out of the Power6 designs. Somewhere between 30 percent and 45 percent more work for a 114 percent increase in clock speed just does not seem like a smart trade--or a fair one. Particularly when all of IBM's competitors are throwing four or eight cores on a chip and trying to lower clock speeds to save on heat and to get memory and CPU speeds closer to each other and thereby boost the efficiency of their processors.
This approach, from IBM's point of view, has two problems. It presupposes that applications are multithreaded and can spread work out over more cores. Batch jobs and single-threaded RPG, COBOL, and C++ applications can't take as much advantage of extra cores.
Of course, not all problems can be parallelized, so there will still be demand for chips with high single-thread performance and few cores (POWER6 has two).
But presumably, the market for multi-core chips will grow faster, now that Intel and AMD are going multi-core (AMDs 4-Core Barcelona should be here in September).
IBM's decision to still go with only to cores per chip, seems strange, as they were the first ones to bring dual-core CPUs to the market.
